ASIC Engineer Intern, Design Verification

This role is based in Bangalore, India.

Responsibilities:

• Develop tests, checkers, and coverage to help verify designs.
• Understand the architecture and microarchitecture of designs.
• Use SystemVerilog/UVM/C code to generate test content.
• Develop scripts to automate various processes.
• Debug test failures and collaborate with design and verification teams.
• Contribute to improving verification processes and methodology.

Minimum Qualifications:

• Currently pursuing a Bachelor's degree in Electrical Engineering, Computer Engineering, or related fields.
• Knowledge of Computer Architecture and Logic Design fundamentals.
• Critical and creative problem-solving skills.
• Work authorization in the country of employment at the time of hire.
• Intent to return to degree program after the internship.

Preferred Qualifications:

• Pursuing a Master's or PhD degree in related fields.
• Knowledge of SystemVerilog/VHDL/Verilog.
• Scripting experience with Python or Perl.